Design Issues of CMOS VCO for RF Transceivers

서지정보

· 발행기관 : 한국전자파학회
· 수록지 정보 : Journal of Electromagnetic Engineering and Science / 9권 / 1호 / 25 ~ 30페이지
· 저자명 : 류성한

초록

This paper describes CMOS VCO circuit design procedures and techniques for multi-band/multi-standard RF transceivers. The proposed techniques enable a 4 GHz CMOS VCO to satisfy all requirements for Quad-band GSM/EDGE and WCDMA standards by achieving a good trade-off among important specifications, phase noise, power consumption, modulation performance, and chip area efficiency. To meet the very stringent GSM T/Rx phase noise and wide frequency range specifications, the VCO utilizes bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain(30～50 MHz/V) and an on-chip 2nd harmonic noise filter. The proposed VCO is implemented in 0.13 μm CMOS technology. The measured tuning range is about 34 %(3.17 to 4.49 GHz). The VCO exhibits a phase noise of －123 dBc/Hz at 400 kHz offset and －145 dBc/Hz at 3 MHz offset from a 900 MHz carrier after LO chain. The calculated figure of merit(FOM) is －183.5 dBc/Hz at 3 MHz offset. This fully integrated VCO occupies 0.45×0.9 ㎟.

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