디지털시계
- 최초 등록일
- 2012.08.05
- 최종 저작일
- 2012.08
- 7페이지/
MS 워드
- 가격 3,000원
소개글
디지털 시계를 verilog rtl 레벨로 코딩해보았습니다.
컴파일 실행환경
Verilog
본문내용
module watch(clk,clk_1, rst, btnA, btnB, hourH, hourL, minH,minL,secH,secL,sec_cnt1);
input clk;
input clk_1;
input rst;
input btnA;
input btnB;
output [3:0] hourH; // except dot signal
output [3:0] hourL;
output [3:0] minH; // except dot signal
output [3:0] minL;
output [3:0] secH;
output [3:0] secL;
output [3:0] sec_cnt1;
wire sec_co,min_co ;
wire [3:0] sec_cnt1,min_cnt1 ;
wire [2:0] sec_cnt10,min_cnt10 ;
wire [3:0] hour_cnt1;
wire [1:0] hour_cnt10;
assign secL = sec_cnt1; //4bit BCD code
assign secH = {1`b0,sec_cnt10};
assign minL = min_cnt1;
assign minH = {1`b0,min_cnt10};
assign hourL = hour_cnt1;
assign hourH = {2`b0,hour_cnt10};
controller U1(
.clk(clk),
.rst(rst),
.btnA(btnA),
.btnB(btnB),
.Enable(Enable)
);
mod_60 U2 (clk,clk_1,rst,Enable,sec_cnt1,sec_cnt10,sec_co );
mod_60 U3 (sec_co,clk_1,rst,Enable,min_cnt1,min_cnt10,min_co );
mod_24 U4 (min_co,clk_1,rst,Enable,hour_cnt1,hour_cnt10,hour_co );
endmodule
참고 자료
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