전기전자기초실험 Flip-flop and Counter Design 결과보고서
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연세대학교 전기전자기초실험 10장 보고서(영문)
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참고자료로 사용하세요
목차
-Objective
-Procedure
1. J-K Flip-flop
2. D Flip-flop
3. Master/Slave J-K Flip-flop
4. 4-bit bi-directional shift register
5. Synchronous mod-10 counter
6. 4-bit Up/down preset counter
-Result
1. Refer to the table and waveform written during the experiment and explain the operations of Master/Slave JK Flip-flop, 4-bit bi-directional shift register, synchronous mod-10 counter circuit, and 4-bit Up/down preset counter.
2. Explain the setup time, hold time in D Flip-flop.
3. Find out the application of Flip-flops.
- Reference
본문내용
-Objective : To understand the operating principle of various kinds of flip-flops, and design counter based on that knowledge.
중략..
-Result
1. Refer to the table and waveform written during the experiment and explain the operations of Master/Slave JK Flip-flop, 4-bit bi-directional shift register, synchronous mod-10 counter circuit, and 4-bit Up/down preset counter.
‣ Master/Slave JK Flip-flop
Each master and slave are consist of JK flip-flop so that it operates same by input value of J and K. Master/Slave flip-flop has the form of slave connecting with output part of master. So output of master influences input of slave. It operates as positive edge clock. It means that whenever clock varies 0 to 1, JK flip-flop is operating. The output Q and QN connect the output part of slave, so slave flip-flop operate as negative edge clock. When clock varies 1 to 0, output comes out. The delay value are 11.5ns and 12.6ns.
참고 자료
♣ Electric Circuit Experiment : Logic Circuit
♣ Contemporary Logic Design 2nd Edition (Randy H. Katz)
